Hi,ENGINEERZ

Weighted Space Time Turbo Trellis Codes

Researchers: Branka Vucetic, Yohghui Li, Jinhong
Yuan and Agus Santoso
Support: ARC Discovery Grant, Norman I Price
Scholarship and Girling Watson Fellowship
Space-time coding, carried out in both the time and space
domains, is a practical technique that enables to approach
the MIMO system capacity bounds. The simplest example
of space-time coding is the Alamouti scheme, which has
been adopted as a standard for the third generation of WCDMA
cellular radio networks and IEEE 802.16
broadband wireless access systems. It is simple to
implement but has no coding gain and its performance is
far from the MIMO system capacity limit. Space-time
trellis codes achieve substantial coding and diversity
gains and are simple to implement for small numbers of
transmit antennas. Layered space-time codes (LST), with
time domain coding only, achieve high coding and
diversity gains but the detection/decoding is quite
challenging for a large number of transmit antennas.
Space-time turbo trellis coded modulation schemes,
outperform the other known ST codes. All these space-
Telecommunications Laboratory
time coding schemes use channel state information (CSI)
at the receiver only. Substantial further improvements are
possible by exploiting CSI both at the transmitter and the
receiver, as demonstrated in our recent results in MIMO
systems with transmit antenna selection. In this project
the performance and design of space-time turbo trellis
codes with variable power across transmit antennas if
both full and partial CSI are available at the transmitter
will be investigated.

EDA is divided into many (sometimes overlapping) sub-areas. They mostly align with the path of manufacturing from design to mask generation. The following applies to chip/ASIC/FPGA construction but is very similar in character to the areas of printed circuit board design:

Design and architecture: design the chip's schematics, output in Verilog, VHDL, SPICE and other formats.
Floorplanning: The preparation step of creating a basic die-map showing the expected locations for logic gates, power & ground planes, I/O pads, and hard macros. (This is analogous to a city-planner's activity in creating residential, commercial, and industrial zones within a city block.)
Logic synthesis: translation of a chip's abstract, logical RTL-description (often specified via a hardware description language, or "HDL", such as Verilog or VHDL) into a discrete netlist of logic-gate (boolean-logic) primitives.
Behavioral synthesis, high-level synthesis or algorithmic synthesis: This takes the level of abstraction higher and allows automation of the architecture exploration process. It involves the process of translating an abstract behavioral description of a design to synthesizable RTL. The input specification is in languages like behavioral VHDL, algorithmic SystemC, C++ etc and the RTL description in VHDL/Verilog is produced as the result of synthesis.
Intelligent verification
Co-design: The concurrent design, analysis or optimization of two or more electronic systems. Usually the electronic systems belong to differing substrates such as multiple PCBs or Package and Chip co-design.
Intelligent testbench
IP cores: provide pre-programmed design elements.
EDA databases: databases specialized for EDA applications. Needed since historically general purpose DBs did not provide enough performance.
Simulation: simulate a circuit's operation so as to verify correctness and performance.
Transistor simulation – low-level transistor-simulation of a schematic/layout's behavior, accurate at device-level.
Logic simulation – digital-simulation of an RTL or gate-netlist's digital (boolean 0/1) behavior, accurate at boolean-level.
Behavioral Simulation – high-level simulation of a design's architectural operation, accurate at cycle-level or interface-level.
Hardware emulation – Use of special purpose hardware to emulate the logic of a proposed design. Can sometimes be plugged into a system in place of a yet-to-be-built chip; this is called in-circuit emulation.
Clock Domain Crossing Verification (CDC check): Similar to linting, but these checks/tools specialize in detecting and reporting potential issues like data loss, meta-stability due to use of multiple clock domains in the design.
Formal verification, also model checking: Attempts to prove, by mathematical methods, that the system has certain desired properties, and that certain undesired effects (such as deadlock) cannot occur.
Equivalence checking: algorithmic comparison between a chip's RTL-description and synthesized gate-netlist, to ensure functional equivalence at the logical level.
Power analysis and optimization: optimizes the circuit to reduce the power required for operation, without affecting the functionality.
Place and route, PAR: (for digital devices) tool-automated placement of logic-gates and other technology-mapped components of the synthesized gate-netlist, then subsequent routing of the design, which adds wires to connect the components' signal and power terminals.
Static timing analysis: Analysis of the timing of a circuit in an input-independent manner, hence finding a worst case over all possible inputs.
Transistor layout: (for analog/mixed-signal devices), sometimes called polygon pushing – a prepared-schematic is converted into a layout-map showing all layers of the device.
Design for Manufacturability: tools to help optimize a design to make it as easy and cheap as possible to manufacture.
Design closure: IC design has many constraints, and fixing one problem often makes another worse. Design closure is the process of converging to a design that satisfies all constraints simultaneously.
Analysis of substrate coupling.
Power network design and analysis
Physical verification, PV: checking if a design is physically manufacturable, and that the resulting chips will not have any function-preventing physical defects, and will meet original specifications.
Design rule checking, DRC – checks a number of rules regarding placement and connectivity required for manufacturing.
Layout versus schematic, LVS – checks if designed chip layout matches schematics from specification.
Layout extraction, RCX – extracts netlists from layout, including parasitic resistors (PRE), and often capacitors (RCX), and sometimes inductors, inherent in the chip layout.
Mask data preparation, MDP: generation of actual lithography photomask used to physically manufacture the chip.
Resolution enhancement techniques, RET – methods of increasing of quality of final photomask.
Optical proximity correction, OPC – up-front compensation for diffraction and interference effects occurring later when chip is manufactured using this mask.
Mask generation – generation of flat mask image from hierarchical design.
Manufacturing test
Automatic test pattern generation, ATPG – generates pattern-data to systematically exercise as many logic-gates, and other components, as possible.
Built-in self-test, or BIST – installs self-contained test-controllers to automatically test a logic (or memory) structure in the design
Design For Test, DFT – adds logic-structures to a gate-netlist, to facilitate post-fabrication (die/wafer) defect testing.
Technology CAD, or TCAD, simulates and analyses the underlying process technology. Semiconductor process simulation, the resulting dopant profiles, and electrical properties of devices are derived directly from device physics.
Electromagnetic field solvers, or just field solvers, solve Maxwell's equations directly for cases of interest in IC and PCB design. They are known for being slower but more accurate than the layout extraction above.

Electronic design automation (EDA) is the category of tools for designing and producing electronic systems ranging from printed circuit boards (PCBs) to integrated circuits. This is sometimes referred to as ECAD (electronic computer-aided design) or just CAD. (The articles for Printed circuit boards and wire wrap both contain specialized discussions of the EDA used for those.)

Terminology

The term EDA is also used as an umbrella term for computer-aided engineering, computer-aided design and computer-aided manufacturing of electronics in the discipline of Electronic engineering. This usage probably originates in the IEEE Design Automation Technical Committee.

This article describes EDA specifically for electronics, and concentrates on EDA used for designing integrated circuits. The segment of the industry that must use EDA are chip designers at semiconductor companies. Large chips are too complex to design by hand.

Growth of EDA

EDA for electronics has rapidly increased in importance with the continuous scaling of semiconductor technology.[citation needed] Some users are foundry operators, who operate the semiconductor fabrication facilities, or "fabs", and design-service companies who use EDA software to evaluate an incoming design for manufacturing readiness. EDA tools are also used for programming design functionality into FPGAs.

Outside plant (OSP) engineers are also often called Field Engineers as they often spend a great deal of time in the field taking notes about the civil environment, aerial, above ground, and below ground. OSP Engineers are responsible for taking plant (copper, fiber, etc.) from a wire center to a distribution point or destination point directly. If a distribution point design is used then a cross connect box is placed in a strategic location to feed a determined distribution area.

The cross-connect box, also known as a service area interface is then installed to allow connections to be made more easily from the wire center to the destination point and ties up fewer facilities by not having dedication facilities from the wire center to every destination point. The plant is then taken directly to its destination point or to another small closure called a pedestal where access can also be gained to the plant if necessary. These access points are preferred as they allow faster repair times for customers and save telephone operating companies large amounts of money.

The plant facilities can be delivered via underground facilities, either direct buried or through conduit or in some cases laid under water, via aerial facilities such as telephone or power poles, or via microwave radio signals for long distances where either of the other two methods is too costly.

As structural engineers, OSP egineers are responsible for the structural design and placement of cellular towers and telephone poles as well as calculating pole capabilities of existing telephone or power poles new plant is being added onto. Structural calculations are required when boring under heavy traffic areas such as highways or when attaching to other structures such as bridges. Shoring also has to be taken into consideration for larger trenches or pits. Conduit structures often include encasements of slurry that needs to be designed to support the structure and withstand the environment around it (soil type, high traffic areas, etc.).

As electrical engineers, OSP engineers are responsible for the resistance, capacitance, and inductance (RCL) design of all new plant to ensure telephone service is clear and crisp and data service is clean as well as reliable. Attenuation and loop loss calculations are required to determine cable length and size required to provide the service called for. In addition power requirements have to be calculated and provided for to power any electronic equipment being placed in the field. Ground potential has to be taken into consideration when placing equipment, facilities, and plant in the field to account for lightning strikes, high voltage intercept from improperly grounded or broken power company facilities, and from various sources of electromagnetic interference.

As civil engineers, OSP egineers are responsible for drawing up plans, either by hand or using Computer Aided Drafting (CAD) software, for how telecom plant facilities will be placed. Often when working with municipalities trenching or boring permits are required and drawings must be made for these. Often these drawings include about 70% or so of the detailed information required to pave a road or add a turn lane to an existing street. Structural calculations are required when boring under heavy traffic areas such as highways or when attaching to other structures such as bridges. As Civil Engineers Telecom Engineers provide the modern communications backbone for all technological communications distributed throughout civilizations today.

Unique to Telecom Engineering is the use of air core cable which requires an extensive network of air handling equipment such as compressors, manifolds, regulators and hundreds of miles of air pipe per system that connects to pressurized splice cases all designed to pressurize this special form of copper cable to keep moisture out and provide a clean signal to the customer.

As Political and Social Ambassador, the OSP Engineer is the telephone operating companies’ face and voice to the local authorities and other utilities. OSP Engineers often meet with municipalities, construction companies and other utility companies to address their concerns and educate them about how the telephone utility works and operates. Additionally, the OSP Engineer has to secure real estate to place outside facilities on such as an easement to place a cross connect box on.

A telecom equipment engineer is an electronics engineer that designs equipment such as routers, switches, multiplexers, and other specialized computer/electronics equipment designed to be used in the telecommunication network infrastructure.

Central-office engineer

A Central-office engineer is responsible for designing and overseeing the implementation of telecommunications equipment in a central office (CO for short), also referred to as a wire center or telephone exchange. A CO engineer is responsible for integrating new technology into the existing network, assigning the equipments location in the wire center and providing power, clocking (for digital equipment) and alarm monitoring facilities for the new equipment. The CO engineer is also responsible for providing more power, clocking, and alarm monitoring facilities if there isn’t currently enough available to support the new equipment being installed. Finally, the CO Engineer is responsible for designing how the massive amounts of cable will be distributed to various equipment and wiring frames throughout the wire center and overseeing the installation and turn up of all new equipment.

As structural engineers, CO engineers are responsible for the structural design and placement of racking and bays for the equipment to be installed in as well as for the plant to be placed on.

As electrical engineers, CO engineers are responsible for the resistance, capacitance, and inductance (RCL) design of all new plant to ensure telephone service is clear and crisp and data service is clean as well as reliable. Attenuation and loop loss calculations are required to determine cable length and size required to provide the service called for. In addition power requirements have to be calculated and provided for to power any electronic equipment being placed in the wire center.

Telecommunications engineering or telecom engineering is a major field within electronic engineering. Telecom engineers come in a variety of different types from basic circuit designers to strategic mass developments. A telecom engineer is responsible for designing and overseeing the installation of telecommunications equipment and facilities, such as complex electronic switching systems to copper telephone facilities and fiber optics. Telecom engineering also overlaps heavily with broadcast engineering.

Telecommunications is a diverse field of engineering including electronics, civil, structural, and electrical engineering as well as being a political and social ambassador, a little bit of accounting and a lot of project management. Ultimately, telecom engineers are responsible for providing the method that customers can get telephone and high speed data services.

Telecom engineers use a variety of different equipment and transport media available from a multitude of manufacturers to design the telecom network infrastructure. The most common media, often referred to as plant in the telecom industry, used by telecommunications companies today are copper, coaxial cable, fiber, and radio.

Telecom engineers are often expected, as most engineers are, to provide the best solution possible for the lowest cost to the company. This often leads to creative solutions to problems that often would have been designed differently without the budget constraints dictated by modern society. In the earlier days of the telecom industry massive amounts of cable were placed that were never used or have been replaced by modern technology such as fiber optic cable and digital multiplexing techniques.

Telecom engineers are also responsible for keeping the records of the companies’ equipment and facilities and assigning appropriate accounting codes for purposes of taxes and maintenance. As telecom engineers responsible for budgeting and overseeing projects and keeping records of equipment, facilities and plant the telecom engineer is not only an engineer but an accounting assistant or bookkeeper (if not an accountant) and a project manager as well.

Formation of petroleum occurs from hydrocarbon pyrolysis, in a variety of mostly endothermic reactions at high temperature and/or pressure.[15] Today's oil formed from the preserved remains of prehistoric zooplankton and algae, which had settled to a sea or lake bottom in large quantities under anoxic conditions (the remains of prehistoric terrestrial plants, on the other hand, tended to form coal). Over geological time the organic matter mixed with mud, and was buried under heavy layers of sediment resulting in high levels of heat and pressure (diagenesis). This process caused the organic matter to change, first into a waxy material known as kerogen, which is found in various oil shales around the world, and then with more heat into liquid and gaseous hydrocarbons via a process known as catagenesis.