Hi,ENGINEERZ

EDA is divided into many (sometimes overlapping) sub-areas. They mostly align with the path of manufacturing from design to mask generation. The following applies to chip/ASIC/FPGA construction but is very similar in character to the areas of printed circuit board design:

Design and architecture: design the chip's schematics, output in Verilog, VHDL, SPICE and other formats.
Floorplanning: The preparation step of creating a basic die-map showing the expected locations for logic gates, power & ground planes, I/O pads, and hard macros. (This is analogous to a city-planner's activity in creating residential, commercial, and industrial zones within a city block.)
Logic synthesis: translation of a chip's abstract, logical RTL-description (often specified via a hardware description language, or "HDL", such as Verilog or VHDL) into a discrete netlist of logic-gate (boolean-logic) primitives.
Behavioral synthesis, high-level synthesis or algorithmic synthesis: This takes the level of abstraction higher and allows automation of the architecture exploration process. It involves the process of translating an abstract behavioral description of a design to synthesizable RTL. The input specification is in languages like behavioral VHDL, algorithmic SystemC, C++ etc and the RTL description in VHDL/Verilog is produced as the result of synthesis.
Intelligent verification
Co-design: The concurrent design, analysis or optimization of two or more electronic systems. Usually the electronic systems belong to differing substrates such as multiple PCBs or Package and Chip co-design.
Intelligent testbench
IP cores: provide pre-programmed design elements.
EDA databases: databases specialized for EDA applications. Needed since historically general purpose DBs did not provide enough performance.
Simulation: simulate a circuit's operation so as to verify correctness and performance.
Transistor simulation – low-level transistor-simulation of a schematic/layout's behavior, accurate at device-level.
Logic simulation – digital-simulation of an RTL or gate-netlist's digital (boolean 0/1) behavior, accurate at boolean-level.
Behavioral Simulation – high-level simulation of a design's architectural operation, accurate at cycle-level or interface-level.
Hardware emulation – Use of special purpose hardware to emulate the logic of a proposed design. Can sometimes be plugged into a system in place of a yet-to-be-built chip; this is called in-circuit emulation.
Clock Domain Crossing Verification (CDC check): Similar to linting, but these checks/tools specialize in detecting and reporting potential issues like data loss, meta-stability due to use of multiple clock domains in the design.
Formal verification, also model checking: Attempts to prove, by mathematical methods, that the system has certain desired properties, and that certain undesired effects (such as deadlock) cannot occur.
Equivalence checking: algorithmic comparison between a chip's RTL-description and synthesized gate-netlist, to ensure functional equivalence at the logical level.
Power analysis and optimization: optimizes the circuit to reduce the power required for operation, without affecting the functionality.
Place and route, PAR: (for digital devices) tool-automated placement of logic-gates and other technology-mapped components of the synthesized gate-netlist, then subsequent routing of the design, which adds wires to connect the components' signal and power terminals.
Static timing analysis: Analysis of the timing of a circuit in an input-independent manner, hence finding a worst case over all possible inputs.
Transistor layout: (for analog/mixed-signal devices), sometimes called polygon pushing – a prepared-schematic is converted into a layout-map showing all layers of the device.
Design for Manufacturability: tools to help optimize a design to make it as easy and cheap as possible to manufacture.
Design closure: IC design has many constraints, and fixing one problem often makes another worse. Design closure is the process of converging to a design that satisfies all constraints simultaneously.
Analysis of substrate coupling.
Power network design and analysis
Physical verification, PV: checking if a design is physically manufacturable, and that the resulting chips will not have any function-preventing physical defects, and will meet original specifications.
Design rule checking, DRC – checks a number of rules regarding placement and connectivity required for manufacturing.
Layout versus schematic, LVS – checks if designed chip layout matches schematics from specification.
Layout extraction, RCX – extracts netlists from layout, including parasitic resistors (PRE), and often capacitors (RCX), and sometimes inductors, inherent in the chip layout.
Mask data preparation, MDP: generation of actual lithography photomask used to physically manufacture the chip.
Resolution enhancement techniques, RET – methods of increasing of quality of final photomask.
Optical proximity correction, OPC – up-front compensation for diffraction and interference effects occurring later when chip is manufactured using this mask.
Mask generation – generation of flat mask image from hierarchical design.
Manufacturing test
Automatic test pattern generation, ATPG – generates pattern-data to systematically exercise as many logic-gates, and other components, as possible.
Built-in self-test, or BIST – installs self-contained test-controllers to automatically test a logic (or memory) structure in the design
Design For Test, DFT – adds logic-structures to a gate-netlist, to facilitate post-fabrication (die/wafer) defect testing.
Technology CAD, or TCAD, simulates and analyses the underlying process technology. Semiconductor process simulation, the resulting dopant profiles, and electrical properties of devices are derived directly from device physics.
Electromagnetic field solvers, or just field solvers, solve Maxwell's equations directly for cases of interest in IC and PCB design. They are known for being slower but more accurate than the layout extraction above.